Within the realm of semiconductor manufacturing technology, the trend toward ever-increasing device density, accompanied by corresponding decreases in device dimensions seems unlikely to abate in the foreseeable future.
FIG. 1 is a cross-section of the isolation geometry that is created for high-performance MOS arrays utilizing a process known as LOCal Oxidation of Silicon (LOCOS). LOCOS has become the standard device isolation technique, due to the semi-recessed topography of the field oxide 11, low defect density, and the self-aligning nature of the field implant in the n-channel field regions 13. However, with conventional LOCOS technology, precious array area is wasted in the thin-to-thick oxide transition regions known as the "bird's beak" regions 15. The very gradual slope of the bird's beak region not only wastes space, but also hampers subsequent fine-line lithography operations which, for VLSI devices, is best suited to planar surface topography.
The loss of array area in the bird's beak regions is exacerbated by the lateral diffusion of the field implant into the active areas 17. As a result of this phenomenon, the substrate doping is effectively increased in the encroachment region 19 near field edges. Consequently, threshold voltage increases near device edges, and the full device width is unavailable for source-drain current. The usual manifestation of this "narrow channel effect" is an increase in apparent device threshold voltage as the channel width decreases.
If higher packing densities are to be achieved for VLSI devices, it is clear that future approaches to isolation technology must reduce both physical and electrical encroachment and achieve a greater degree of topography planarity. A number of approaches have been proposed as either an alternative or a modification to the LOCOS process.
One of the more basic improvements to LOCOS which results in somewhat more planar surface topography and a reduction in the size of the bird's beak region is the etchback process. The cross-sectional geometry resulting from this process is depicted in FIG. 2. The effectiveness of this technique, however, is limited by two factors--an increase in the effective size of the field implant encroachment region 19 and the degree of remaining surface nonplanarity following the etchback.
Another simple modification to LOCOS, dubbed SILO, results in the cross-sectional profile depicted in FIG. 3. A thin silicon nitride film formed by plasma nitridation or ion implantation is used to either replace or underlay the usual silicon nitride-silicon oxide bilayer used for conventional LOCOS. Although the fabrication process is complicated somewhat by some extra wet cleaning steps, the bird's beak region is reduced in size and lateral field encroachment region is reduced in size because of the reduced temperature cycle needed to grow the field oxide.
Several of the problems associated with LOCOS were ameliorated with a Side Wall Masked Isolation (SWAMI) technique developed at Hewlett Packard Laboratories. The field isolation geometry depicted in FIG. 4 is characteristic of that produced with the SWAMI process. This improvement to LOCOS greatly reduces lateral oxidation and also provides a planar surface topography with steeper oxide-to-silicon isolation boundary 41. However, the SWAMI process adds a great deal of complexity to the fabrication process and can lead to increased defect density.
Another modified LOCOS technique which produces a nearly planar surface topography is the use of potassium hydroxide to etch the field regions prior to thermally growing the oxide. The field isolation geometry depicted in FIG. 5 is representative of that produced with this process. Such a technique results in fully-recessed field oxide regions 11. Unfortunately, lateral oxidation with this technique is greater than with standard LOCOS. Additionally, true planarity is not achieved due to the formation of a "bird's head" 51 during the thermal growth of the field oxide. Bird's head formation is indicative of the existence of stress at the edges of array active areas. Stress can result in crystal lattice locations which increases device defect density.
A new process for creating field isolation regions is needed that provides complete planarity, low defect density, and no bird's beak transition regions at the edge of array active areas.